1. Field of the Invention
This invention relates to a memory management unit for microprocessors, and more particularly, to a circuit configuration of the memory management unit in which logical addresses are translated into physical addresses.
2. Description of the Prior Art
As an example of conventional memory management units, FIG. 4 shows a block diagram of a Zilog in U.S.A.); see S. Kamuro et al., in 16-bit Microprocessors, Chap. 2, pp. 75-155 (Maruzen, 1983). In this figure, reference numeral 1 is a 23-bit logical address transferred from the central processing unit (CPU) that is not shown therein. Reference numeral 2 is a data bus through which 16-bit data is transferred from the CPU to the memory management unit 3 in which logical addresses are translated into physical addresses. Also, reference numeral 4 is a 24-bit physical address; reference numeral 5 is a 16-bit offset address that is a part of the logical address 1 transferred from the CPU; and reference numeral 6 is a 7-bit segment number that is a part of the logical address 1 transferred from the CPU. Moreover, reference numeral 7 is a segment register section that is composed of a plurality of 16-bit segment registers. The address data to be stored in these segment registers is transferred from the CPU through the data bus 2. The segment register in the segment register section 7 is selected according to the 7-bit segment number 6. The 16-bit output data from the selected segment register is placed in a base address register 9. The leftmost 8 bits (A8-A15) of the 16-bit offset address 5 are stored in a temporary register 8. The 8bit output data from the temporary register 8 is added to the 16-bit output data from the base address register 9 by means of an adder 10 to form the leftmost 16 bits of the 24-bit physical address 4, resulting in a segment address 12 in the physical address space. The rightmost 8 bits (AO-A7) of the offset address 5 is used as the rightmost 8 bits of the 24-bit physical address 4, resulting in an offset address 11 within each segment.
FIG. 5 shows a block diagram of another conventional memory management unit that has a great deal of flexibility in the circuit configuration as compared with the memory management unit of FIG. 4. Although the memory management unit of FIG. 5 has a circuit configuration to treat 8-bit data, the basic configuration of the memory management unit for treating 16-bit data or other data with different bit lengths is the same as that shown in FIG. 5. In FIG. 5, reference numeral 101 is a 16-bit logical address transferred from the CPU; reference numeral 102 is an 8-bit data transferred from the CPU; and reference numeral 103 is an address translation unit in which the logical address 101 is translated into the 19-bit physical address 104 to specify the actual memory address. Also, reference numeral 105 is a segment address decoder by which any one of 2.sup.5 (=32) segment registers in the segment register section 106 is selected according to the leftmost 5 bits (A11-A15) of the logical address 101. The 8-bit output data from the selected segment register gives the leftmost 8 bits of the physical address 104, resulting in a segment address 109 in the physical address space. The rightmost 11 bits (AO-A10) of the logical address 101 are used as the rightmost 11 bits of the physical address 104, resulting in an offset address 108 within each segment. Moreover, reference numeral 107, which is not shown definitely in FIG. 5, is a logical operation unit in which some type of logical operation is performed between the output data from the segment register and all or part of the lower address of the logical address 101 transferred from the CPU. The logical operation unit 107 may be any type of logical operation unit, and may be, for example, an adder of the same type as shown in FIG. 4.
In such a conventional addressing arrangement, when a certain segment address is selected in the physical address space, the range of offset address that can be selected freely within each segment according to the address data from the CPU is limited to a fixed range that is determined by the lower part of the physical address. For example, the offset address range contains only 2.sup.8 (=256) addressable locations in the case of the memory management unit shown in FIG. 4, and only 2.sup.11 (=2048) addressable locations in the case of the memory management unit shown in FIG. 5. This limitation of the offset address range within each segment results in a great number of restrictions on the application of such a memory management unit and on the use of microprocessors.